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'''E. [wiki:GraspSw Controller Address Space and Clocking Instructions]''' |
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[[TracNav(GraspContents)]] |
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This is a very low level API, used only by someone writing a newer |
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controller socket level command. All controller socket level |
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commands are implemented in C code (downloaded as the stage2.srec |
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to the controller) which modifies registers or address space, and/or |
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writes instructions to the clocking engine. |
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Our FPGA [wiki:V2P20Phase0HWSWInterface Memory Map] includes [wiki:V2P20GPIO General Purpose I/O (GPIOs)] that |
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allow access to: |
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* Board ID Register Bits |
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* Board I2C Register Bits |
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* ADC SPI Configuration Register Interface |
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* Clocking Engine Register Interface |
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== Board ID Bits == |
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The first generation of STARGRASP controller fpga boards contain a 2 bits in a GPIO register which indicate which slot of a 4 slot chassis the board is in, and 3 more bits which are programmable as a "chassis ID" to differentiate the chassis when used in a mosaic camera or on a network with multiple development systems e.g. in a lab. |
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The current generation of STARGRASP uses more flexible I2C parts so that we can ID each board and store more information than just the chassis number. |
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== Board I2C Bits == |
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(More info needed on all of the things accessible by I2C here.) |
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== ADC SPI Configuration Register == |
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(More information on the ADC needed here.) |
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== Clocking Engine == |
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The "Clocking Engine" is an fpga-hardware pattern generator which we developed specifically for controlling clock lines to read a detector. It consists of one 3-bit pattern generator we call "PG3" and two 4-bit pattern generators we call "PG4s". Each bit in the PG can control one detector clock line signal. |
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