pixtype

Command:	pixtype
Contexts:	Network socket, serial console. Applies only if the CCD is an "OTA" device.
Function:	Tell the controller which pixel structure design the OTA has.
Required Parameters:	type=0|1|2|102|103|104
Optional Parameters:	dev=all|0|1

The following table explains the possible values for the type field:

0	The CCD is not an OTA, and can only shift "up" and "down"
1	The CCD has MITLL OTA Type 1 pixel structure
2	The CCD has MITLL OTA Type 2 pixel structure
102	The CCD is an STA with Type 1 pixel structure but STA phase wiring
103	The CCD is a newer STA device with yet another variation
104	Also for STA, like 103, but with modifications (see below)

MITLL Devices

Original MITLL OTA pixel designs had two types, called "type 1" and "type 2". The basic layout of the parallel phases is illustrated below:

Pixel type 2 was never built. All MITLL CCID58, CCID64, and CCID71 use type 1. Other than the general geometry of the phases, the orientation of the pixel with respect to the serial register, and output are important, as are the connections of parallel standby high (PSH) and low (PSL). The figure below attempts to show all of this for pixel type 1:

Error: Macro Image(phases_ccid64.png) failed

Attachment is missed: module=wiki, id=GraspSwControllerCmdPixtype, file=phases_ccid64.png

The figure shows a device with a 2 phase serial register. CCID58's with 3-phase serial registers have identical parallel structure and therefore use the same type 1 clocking patterns. For all MITLL CCID58, CCID64, CCID71, the correct form is:

pixtype dev=all type=1

After sending this command, the ot command will sequence the parallel phases in the following way for various shifts:

Shift Parameter	Sequencing
shift1p (move image along axis1 toward output)	P1>P2>P4>P1
shift1n (move image along axis1 away from output)	P2>P1>P4>P2
shift2p (move image along axis2 toward serial register)	P1>P2>P3>P1
shift2n (move image along axis2 away from serials)	P2>P1>P3>P2

All patterns start and end with P1+P2 in the high state. This way there are no unwanted clock transitions whenever an OTA cell is taken in or out of standby mode, because P1+P2 are the phases connected to PSH. The phase sequencing in the table above will only result if clvset ppg4= contains a parallel pattern P1>P2>P3>P1 that starts and ends with P1,P2 high. Matching pixtype 1 with anything else is a configuration error (and the code should probably check and warn, but it does not presently do that.)

STA Devices

STA produced several variants which were apparently intended to be a clone of the MITLL type 1 pixel, however the pixel was "flipped" and the parallel phases were numbered differently. In an attempt to deal with this, types "102", "103", and "104" have been created, loosely intended to be used on STA "lot 2", "lot 3" and "lot 4" devices. (If someone has better names for these STA "lots" please update this information.) We believe that the following figure is representative of the two most recent "lots":

Although the layout of the pixel appears to match MITLL type 1, we can only infer that the output is supposed to be on the left while MITLL shows it on the right of their figures. Also, while the central triangular phases are connected to PSH, they are numbered P2 and P3 instead of P1 and P2. As a result the controller clocking engine will need to be configured to generate different waveforms for these devices. We believe that type=102 should not be used unless older devices with additional quirks (which are fixed in the latest lots) are being used. We have had some signs of success with type=103, but added type=104 after realizing that neither type 102 nor 103 were generating patterns which would start and end with P2+P3 high, which would cause unwanted transitions when switching a cell from standby to active. 102 and 103 have been left in so they can be tried for comparison, but we believe 104 should be the best choice for the latest STA devices:

pixtype dev=all type=104

Just as with the MITLL devices, after sending this command, the ot command will sequence the parallel phases in the following way for various shifts:

Shift Parameter	Sequencing
shift1p (move image along axis1 toward output)	P3>P2>P4>P3
shift1n (move image along axis1 away from output)	P2>P3>P4>P2
shift2p (move image along axis2 toward serial register)	P2>P3>P1>P2
shift2n (move image along axis2 away from serials)	P3>P2>P1>P3

All patterns start and end with P2+P3 in the high state. This way there are no unwanted clock transitions whenever an OTA cell is taken in or out of standby mode, because P2+P3 are the phases connected to PSH (versus P1 and P2 in the case of the MITLL OTA.) The phase sequencing in the table above will only result if clvset ppg4= contains a parallel pattern P2>P3>P1>P2 that starts and ends with P2,P3 high. Matching pixtype 103 with anything else is a configuration error (and the code should probably check and warn, but it does not presently do that.)

Notes:

Shifts along axis2 (the normal parallel direction) typically tend to function even if the pixtype setting is wrong. See also ot command.

If dev= is omitted, the last default dev applies (which can be either 0 or 1, but not "all").

Bugs:

Pixtype makes assumptions about ppg4 (parallel clocking pattern) and swaps phases around (e.g., exchanging the states of P1<->P2 to reverse direction) without verifying that such manipulations are valid for the current ppg4 setting. Read carefully the notes for your device type and check your parallel clocking pattern.