E. Controller Address Space and Clocking Instructions
Contents
- STARGRASP Core System
- I. Core System Operation
- II. Core Software Overview
- Command Syntax Notes
- Application Notes
- A. Demo Scripts
- B. Toolkit Level
- C. STARGRASP C Libraries
- D. Controller Socket Commands
- E. Registers and Clocking Instructions
- III. Core Hardware Overview
- IV. Computers and Switches
- V. Test Procedures
- STARGRASP Info-Sheet
- STARGRASP Quick Start
- Extra Software Provided (Unsupported)
This is a very low level API, used only by someone writing a newer controller socket level command. All controller socket level commands are implemented in C code (downloaded as the stage2.srec to the controller) which modifies registers or address space, and/or writes instructions to the clocking engine.
Our FPGA Memory Map? includes General Purpose I/O (GPIOs)? that allow access to:
- Board ID Register Bits
- Board I2C Register Bits
- ADC SPI Configuration Register Interface
- Clocking Engine Register Interface
Todo: Incorporate the wiki pages above into GraspContents.
Related info:
- Clocking Engine Math Module?
- Clocking Engine pattern generator bit packing?
- PDF of clocking engine block diagram attached below.
Attachments
- clocking_engine.gif (26 kB) - , added by isani on Sun Jul 6 11:38:35 2008.
