E. Controller Address Space and Clocking Instructions

This is a very low level API, used only by someone writing a newer controller socket level command. All controller socket level commands are implemented in C code (downloaded as the stage2.srec to the controller) which modifies registers or address space, and/or writes instructions to the clocking engine.

Our FPGA Memory Map? includes General Purpose I/O (GPIOs)? that allow access to:

• Board ID Register Bits
• Board I2C Register Bits
• ADC SPI Configuration Register Interface
• Clocking Engine Register Interface

Board ID Bits

The first generation of STARGRASP controller fpga boards contain a 2 bits in a GPIO register which indicate which slot of a 4 slot chassis the board is in, and 3 more bits which are programmable as a "chassis ID" to differentiate the chassis when used in a mosaic camera or on a network with multiple development systems e.g. in a lab.

The current generation of STARGRASP uses more flexible I2C parts so that we can ID each board and store more information than just the chassis number.

Board I2C Bits

(More info needed on all of the things accessible by I2C here.)

ADC SPI Configuration Register

(More information on the ADC needed here.)

Clocking Engine

The "Clocking Engine" is an fpga-hardware pattern generator which we developed specifically for controlling clock lines to read a detector. It consists of one 3-bit pattern generator we call "PG3" and two 4-bit pattern generators we call "PG4s". Each bit in the PG can control one detector clock line signal.

Todo: Incorporate the wiki pages above into GraspContents.

Related info:

• Clocking Engine Math Module?
• Clocking Engine pattern generator bit packing?
• Clocking engine block diagram attached below.